Zynq ethernet setup 

Zynq ethernet setup. Netmask : 255. 5V test conditions. e. ZyboZ7 Ethernet config. I also confimed that I can transmit valid characters using the uartlite in Nov 3, 2020 · I am having trouble with the setup of the Ethernet port on my PC for the ADRV9002 and XILINX ZYNQ ZC706 combination. 4 netmask 255. Other PHY interfaces can be implemented by using appropriate shim logic in the PL. The expandability features of this evaluation and development platform make it ideal for rapid prototyping and proof-of-concept development. 4），ping命令的时候不通。. I'm basing my implementation on the uartlite driver example uartlite_intr_tapp_example. Hello All, I'm Mark and has been busy working on my Zybo recently. eth0: ethernet@ff0e0000. Test-the-ethernet-KSZ9031-with-lwip-code-created-by-the-EDK but it doesn't mention tool versions and original post is a year ago and no solutions offered, so I start new one but I get the feeling I might not be alone in my KSZ9031/Zynq link struggles. . Get a Zed Board ready to be used with This page provides the details of 2022. The PS and the PL in Zynq UltraScale+ devices can be tightly or loosely coupled with a variety of high-performance and high-bandwidth PS-PL interfaces. 11 using the given netmask. Turn on the PYNQ-Z1 and check the boot sequence by following the Download the PetaLinux 2021. But I cannot find similar settings in my Vivado 2018. So this will forward connections to port <port> to the VM Linux on port 23 (the commonly used Telnet port). The performance improvement achieved in terms of CPU utilization and throughput for TCP and UDP use cases is shared in this page. txt (in src folder) files are needed for the System Device Tree based flow. Details are provi Set this value by using the ifconfig command. 2 on my PC. Sep 14, 2020 · Assign a static IP address to a Zynq board with Koheron OS. Board IP: 192. The slirp IP is the network address on the small internal network (or LAN) that QEMU creates. The hardened cores delivers over 1Gb/s of performance at low latency, as well as lower power and smaller area than soft logic implementations. Xilinx uses U-Boot as a second stage boot loader in the Zynq-7000 devices. Zynq-7000 has a consistent Processing System (PS) throughout the family but the Programmable Logic (PL) utilizes the Artix-7 for the Cost-Optimized Devices and utilizes the Kintex-7 for the Mid-Range Devices in the family (see below). There are 6 available designs: pl_eth_1g - PL 1000BASE-X design utilizing the AXI Ethernet 1G/2. 2 software from the Xilinx website. NOTE: An administrator account on your laptop/PC might be necessary to complete the install. See below for details on logging on with a terminal. I found this Zynq-7000 forum entry with pictures showing how to set MIO pins as reset pins. 255. Turn on the PYNQ-Z1 and check the boot sequence by following the Connect the 12V power cable. Apr 6, 2017 · ZYBO is configured as a TCP server listening on port 7. Board should be powered off at the start of these instructions. Configuring the DDR Controller in a Zynq UltraScale+ MPSoC. % sudo ifconfig eth Z 192. tcl and . Aug 25, 2021 · I'm looking to set up a MicroBlaze in a Zynq device, whereas the linked document is a "Hello World" for either a MicroBlaze in a device without the Zynq PS or the A9 core in a device with the Zynq PS. Sep 24, 2018 · Set up target and TFTP server IP addresses 3. This kit features a Zynq™ UltraScale+™ MPSoC EV device with video codec and supports many common peripherals and interfaces for embedded vision use case. When the bitstream is successfully generated, select File->Export->Export Run the Connection Automation Tool. Change the following parameters in zynq_common. exe process is allowed through the firewall. PHY Reset. On the site [1] is described that, the Zynq-7000 AP SoC has an in-built DUAL Giga bit Ethernet controllers which can support 10/100/1000 Mb/s EMAC configurations compatible with the IEEE 802. 2），跟踪初始化过程，走zynq_gem通用phy流程。. org) and What exactly is this and how do I connect it? Do I need to bring out the MDIO signals from the IP and route them somehow to the MDIO2 interface, or I just keep them blank here, and handle the configuration for MDIO2 in the software setup? Thank you in advance! CONFIG. The SW6 default position is QSPI32. bat batch file. GMII through the EMIO interface. Connect to power and the board’s 6-pin power supply (J52) and power on board. Quote:" The Gigabit Ethernet Controller (GEM) implements a 10/100/1000 Mb/s Ethernet MAC compatible. 4 ("Configure the PHY") in the ZYNQ manual. 5G Ethernet Subsystem) is quite bare bones and I don't see how to configure it for the Zybo. This demonstration will introduce you to the configuration of the DDR controller in the Zynq® UltraScale+™ MPSoC and highlights the use of the DDR Configuration menu in the Re-customize IP dialog box for the Zynq UltraScale+ MPSoC. 2) Click the Run Block Automation link and click OK. ps7-ethernet: eth0: no PHY setup root@xbpm:~ # ifconfig eth0 Link encap:Ethernet HWaddr 00:0A:35:00:A6:E5 UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1 RX packets:0 errors:0 dropped:0 overruns:0 frame:0 TX packets:6 errors:0 dropped:0 overruns:0 Thank you. Ethernet link becomes Up and Down Frequently | Zynq 7z020 CPU. Select Run Block Automation highlighted in blue. 3. (The switch only has PHYs on ports 0-4) We have been unable so far to use this interface. This application note describes using the processing system (PS) based gigabit Ethernet MAC (GEM) through the extended multiplexed I/O (EMIO) interface with the 1000BASE-X physical interface using high-speed serial transceivers in programmable logic (PL). when I run the old program in the zynq board I get the following out put in UART and internet works fine SystemPlatform: Initialize SystemPlatform: SetupInterrupts SystemPlatform: EnableInterrupt New OpReg: 0x000002a0 link speed: 100----- IP configuration :----- MAC ADDRESS : 42. 8V, 2. Connect your USB WiFi Dongle or Ethernet cable by following the instructions below. Double-click "Setup_RF_DC_Evaluation_UI. Verify hardware setup—see User Guides for each board above. The default configuration receives the IP address through the bootargs string at boot time. Zynq UltraScale＋ RFSoC Power Advantage Tool 2018. (Optional) Connect the USB cable to your PC/Laptop, and to the USB JTAG UART MicroUSB port on the board. Connect the 12V power cable. For more information about U-Boot visit their page at https://www. 2) The connection automation tool will add the required logic blocks for the demo. Optional: see Change the Hostname below. Add common system packages and libraries to the workstation or virtual machine. Connect your USB Wifi Dongle, or Ethernet cable by following the instructions below. Turn on the PYNQ-Z1 and check the boot sequence by following the Nov 25, 2019 · The focus of this application note is on Ethernet peripherals in the Zynq®-7000 SoC. In (DS925) table 44, we have listed switching characters under 2. Turn on the PYNQ-Z1 and check the boot sequence by following the Edited by User1632152476299482873 September 25, 2021 at 3:32 PM. Connect your computer to Ethernet or WiFi on the router/switch. I'm working with a Zybo Z7 development board and trying to implement Ethernet. Connect the Ethernet port by following the instructions below. 5），Ping一次的 Thanks, it works But there is another problem. JTAG: Trying to boot script at 20000000 # # Executing script at 20000000. Browse to http:/ /<board IP address>. We have a custom Zynq 7045-based board which includes a Marvell 88E6352 switch. My goal is to implement a SDN device, so my first step is try to use the PS of Zynq to receive 1 packet and transmit the same packet back. Configure the SW6 switch. IMPORTANT NOTE: A rule must be set up for every installed version of MATLAB that you intend to use with Zynq hardware. Digilent Technical Forums. SD-FEC. 0-147-generic #196-Ubuntu SMP Wed May 2 15:51:34 UTC 2018 x86_64 NIC (1 0G Solarflare's SFN6322F Dual-Port 10GbE SFP+ Adapter) : Default Performance benchmarking Pre-requisites: Set Ethernet MCDMA TX interrupt affinity to core-1 3. - I build my hardware in Vivado 2014. exe". The . When using ports that use Zynq GEM, the BSP setting use_axieth_on_zynq must be set to 0. Turn on the PYNQ-Z2 and check the boot sequence by following the instructions below. 13. Note that the connector is keyed and can only be connected in one way. You can successfully transmit frames using the example application with the Zybo board by simply introducing a wait of the auto-negotiation completion. Check your network environment, first. This repository contains ZCU102 design files for PS and PL based 1G/10G Ethernet on a rolling release. The board IP address is: 192. There seems to be a conflict with the required IPv4 address of 192. Feb 28, 2014 · Run a Simulink Model on Zynq: ZedBoard Set Up (2 of 4) Get a ZedBoard™ ready to be used with MATLAB ® and Simulink ®. Info. FPGA. 0 It is crucial to configure the Host PC that way so that it can connect to the ZYNQ board; The ZYNQ-board has an pre-supplied IP of 10. 2) Click the Run Block Automation link. ZYNQ上的Ethernet无法运行Echo Sever. MQTT-SN is implemented on this overlay, leveraging the scapy python library. 3-2008 standard. Click next and select the options you desire ping 192. The XC7Z020 SoC consists of an SoC-style integrated processing system (PS) and programmable logic (PL) on a single die. @mhedhie5 You are correct that the 10 Gigabit Ethernet Subsystem Product Guide (PG157; v3. Nov 25, 2019 · The Ethernet DMA controller is attached to the FIFO to provide a scatter-gather capability for packet data storage in a Zynq processing system. Connect directly to a computer (Static IP): Assign a static IP address. Connect the USB cable to your PC/Laptop, and to the PROG - UART / J14 MicroUSB port on the board. 2、问题: u-Boot下网络功能测试不通。. Click Generate bitstream. I want to us the eth0/1 parts of the PS through a "PMA/PCS or SGMII" block in the PL, but have been unable to get this to work Hi, I tried migrating the program from old xilinx tools to new. It is very clear on that, and the instructions do not work for the ZedBoard if you want to set up a MicroBlaze along side the Zynq PS. This behavior is observed most of time, i. The processing system (PS) is equipped with four gigabit Ethernet controllers. net). 2) OS : Linux 3. Sep 26, 2018 · configure the ethernet port on the host PC to have an IP address of 10. For more information, see the Installation Requirements from the PetaLinux Tools Documentation: Reference Guide Insert the Micro SD card loaded with the PYNQ-Z2 image into the Micro SD card slot underneath the board. ClockSelection Here is the last line of the boot process NET: Registered protocol family 10 xemacps e000b000. Hello, We are running Linux 3. If using JTAG, connect the FPGA board to the host computer by using a JTAG cable. If using Ethernet, connect the FPGA board to the host computer by using an Ethernet cable. 89. In our case, we use 10. Check Step 4 of Section 16. In this tech tip, the Zynq Processing system uses programmable logic (PL) BRAMS for storing packet control and packet data information coming from PS MAC. To implement the HDL Verifier™ Support Package for Xilinx® FPGA Boards features, you must configure the host computer and the hardware for proper communication. The another option is to use the UART to download the data. An ethernet link becomes Up and Down frequently after power on/reboot. At the other end cable is connected with computer and I'm using static IP configuration. Jul 3, 2018 · The firewall does not block the IP addresses that the development computer and Zynq board use to communicate. In [6] is described in Section Gigabit Ethernet Controller 16. These reference designs can be used with the stand-alone lwIP echo server application template that is part of Vitis; however, some modifications are required. One additional thing to notice is that the example application was probably written for another PHY. 0. The ref guide shows Reset as a zynq output and CLK125 as an input in Fig 5. 2. The example design for the (AXI 1G/2. The ZedBoard includes Xilinx XADC, FMC (FPGA Mezzanine Card), Insert the Micro SD card loaded with the PYNQ-Z2 image into the Micro SD card slot underneath the board. But I cannot connect it through TeraTerm or Putty even if I use fixed IP settings on client side. 1. May 22, 2023 · Although I don't know your network environment, at least it doesn't recognize the Network correctly at Windows side and set the IP address by Windows that can't communicate with the other devices. My block design is simply one block of Zynq7 Processing system with eth0 Apr 20, 2022 · This page gives an overview of how to use the Linux device driver for the Xilinx Zynq UltraScale+ MPSoC PS PCIe End Point DMA functionality. Set mode switch SW6 to 0010 (QSPI32). There you have the choice of setting multiple options, one of which is to obtain a IPv4 address automatically via DHCP. I'm new to Ethernet and have been looking for an example project that utilizes it. de Insert the Micro SD card loaded with the PYNQ-Z1 image into the Micro SD card slot underneath the board. 0 through the MIO interface. To use the sudo command, you might have to enter a password. 231. The Zynq®-7000 SoC comes with a versatile processing system (PS) integrated with a highly flexible and high-performance programmable logic (PL) section, all on a single system-on-a-chip (SoC). with the IEEE 802. Oct 26, 2016 · 1. 5G Ethernet PCS/PMA or SGMII v16. denx. Instructions to set up a Set up a direct ethernet connection between a host and a Zynq board with a static IP address on Windows and Ubuntu. AXILite_Interface false CONFIG. Trying to load boot images from jtag # # Loading init Ramdisk from Legacy Image at 04000000 Image Name: petalinux-initramfs-image-zynqmp Insert the Micro SD card loaded with the appropriate PYNQ image into the MicroSD card slot underneath the board. The driver runs on the host machine on which the end point is connected. The included ZU7EV device is equipped with a quad-core ARM® Cortex™-A53 applications processor, dual-core Cortex-R5 real-time processor, Mali™-400 MP2 graphics processing unit, 4KP60 Insert the Micro SD card loaded with the PYNQ-Z1 image into the Micro SD card slot underneath the board. Traditionally, the PS on ZYNQ board connects to the Ethernet port, while this overlay also bridges the PL on ZYNQ to the Ethernet port. Insert the Micro SD card loaded with the PYNQ-Z1 image into the Micro SD card slot underneath the board. If you modify the BSP's settings in system. 3-2008) and capable of. It seems that I successfully open the server. 0 on a Zynq platform. Currently available shim cores are as follows: I created a preprocessor directive to toggle between enabling uart interrupts and bypass. And the meaning of this IP address is that the same MAC Address exists on the network. . Connect the USB cable to your PC/Laptop, and to the PROG - UART MicroUSB port on the board. Compile the new executable, download it into the Zynq and run it. 2 adding just ZYNQ 7 Processing System IP, apply board presets (from latest MicroZed Board Definition Install for Vivado 2014. See available boot modes below. Starting the Board. 1 Zynq UltraScale+ MPSoC 10G AXI Ethernet Checksum Offload Example design. The GTH transceivers X1Y12-X1Y15 on the Zynq UltraScale+ MPSoC are connected to the SFP cage on the ZCU102 board. Zynq-7000 Analog Data Acquistion using AXI_XADC. 99) Log on to the board through a terminal, and check the system is running, i. 99 (the default static IP address for the board) Continue to Connecting to Jupyter Notebook. 1），kernel下网络功能正常，因此确认硬件ok。. mdd files are for the older build flow which The Gigabit Ethernet Controller in Zynq-7000 SoC supports the following PHY modes: RGMII v2. In this picture is shown 3 possibilities to implement Ethernet-Ports: 1. 我在我的ZYNQ Z7-20开发板上使用Vivado 2021. 6. Hi, I am using the ZyboZ7 to test a prototype a design in Vivado 2018. 我已经开启DHCP功能，但是Uart串口打印DHCP Timeout，并且给 The focus of this application note is on Ethernet peripherals in the Zynq®-7000 SoC. That should be fairly easy to setup but will be rather slow for data transfer. After some time it becomes stable and can take ssh. •. Reference Clock Generation. When the interrupt setup stuff is bypassed, I can ping and talk to the server just fine. pl_eth_sgmii - PL SGMII design utilizing the AXI Ethernet 1G/2. ZYNQ GEM: ff0e0000, mdio bus ff0e0000, phyaddr 12, interface rgmii-id. When using ports that use AXI Ethernet IP, the BSP setting use_axieth_on_zynq must be set to 1. Insert the Micro SD card loaded with the appropriate PYNQ image into the MicroSD card slot underneath the board. Hit any key to stop autoboot: 0 . XAPP1231 - Partial Reconfiguration of a Hardware Accelerator with Vivado Design Suite. In a Zynq UltraScale+ RFSoC device there is a BootROM for initial bring up of the device. Set up a USB serial connection between a host and a Zynq board. 1中创建了Echo Sever例程，并烧录到板子上之后，发现并不能成功运行。. 15 as the IP as this is the IP the DHCP server leases to our VM running Linux. PS -GEM0 is connected to the Marvell PHY through the reduced Add the Zynq IP & GPIO Blocks. that the Linux shell is accessible. yaml (in data folder) and CMakeLists. Download the ZCU102 PetaLinux BSP (ZCU102 BSP (prod-silicon)) from the downloads page. Each. 0 LogiCORE IP Product Guide (PG047) [Ref 2] for more information. Nov 2, 2023 · For further information, refer to the wiki page Porting embeddedsw components to system device tree (SDT) based flow - Xilinx Wiki - Confluence (atlassian. 80 Insert the Micro SD card loaded with the PYNQ-Z2 image into the Micro SD card slot underneath the board. Nov 30, 2021 · Under the Tools & IP tab, Click on “RF Evaluation Tool and Board Setup” to download the software, then unzip the install package in your desired location. The lwIP library needs some modifications to be able to properly configure the Marvell PHYs (88E1510) that are on the Ethernet FMC. Hi @m3atwadtwa1 Ethernet settings can be found in petalinux-config --> Subsystem autohardware settings --> Ethernet settings. Sep 28, 2020 · U-Boot, short for Universal Boot Loader, is an open source, primary boot loader used in embedded devices to boot the device's operating system kernel that is frequently used in the Linux community. 3) Click the Add IP icon again, this time search for “gpio” and add the AXI GPIO core. h if you want different IP addresses. Nov 25, 2019 · The focus of this application note is on Ethernet peripherals in the Zynq®-7000 SoC. Insert the Micro SD card loaded with the PYNQ-Z2 image into the Micro SD card slot underneath the board. Dear all, I am trying to setup bare-metal C application on Zynq 7010 (MicroZed) using LwIP to receive data over the gigabit ethernet (Enet 0) on the PS side. Figure 3: PS-PL Ethernet Design. 3-2008 standard capable of operating in either half or full duplex mode at all three. The Ethernet DMA uses separate transmit and receive lists of buffer descriptors, with each descriptor describing a buffer area in memory Receive Path: The data received by the controller is written to The ZedBoard enables hardware and software developers to create or evaluate Zynq™-7000 All Programmable SoC designs. 1) Click the Add IP button and search for ZYNQ. speeds. 10. （说明：Kernel下网络功能正常）. Turn the power switch to the ON position and check the boot Connect to a Router/Network (DHCP): Connect the Ethernet port on your board to a router/switch. 5V, and 3. 5G Subsystem. Run Vivado and open the project that was just created. In this syntax, ethZ is the name of the host Ethernet port (usually eth 0 , eth 1, and so on). #zynq #ethernet #udp #fpga #vivado #vhdl #verilog #filterZynq 7020 FPGA UDP Communication done through Z turn board. 3、调试过程：. 1 and a subnet mask of 255. Nov 21, 2023 · Implimenting Etherent on the Zybo Z7 development board. 168. The <matlabroot>\bin\matlab. 2 from microzed. 1搭建了含有Ethernet 1的硬件平台，如下图所示. May 6, 2013 · Setup and procedure for redirecting the Ethernet Packet to the PL for Packet Inspection. 5. Sep 24, 2018 · Setup and procedure for redirecting the Ethernet Packet to the PL for Packet Inspection. The Driver . You will find the project in the folder Vivado/<target>. For example, enter this command in the shell. If you can’t ping the board, or the host PC, check your network settings. This will use the board files and correctly configure the ZYNQ processor for the Arty-Z7. operating in either half or full-duplex mode in 10/100 mode and full-duplex in 1000 mode. Turn on the board and check the boot sequence by following the Feb 12, 2019 · All Activity. Double click on ZYNQ7 Processing System to place the bare Zynq block. Zynq 7000 Partial Reconfiguration Reference Design. 从提供的log看，应该是PHY没有被detec到。 可以检查一下PHY的相关电路是否正常，MDIO是否连接，Vivado中MDIO配置是否正确，PHY_RST_N有没有正确释放，时钟正不正常，等等 Zynq Network IP address configuration. In Linux, the recommendation is to always use the provided BSP in your specific tool version to build the design in PetaLinux. 1) states that Zynq-7000 SoC is supported in a minimum of -2 speed grade. This is embedded in the device tree in flash. To change BSP settings: right click on the BSP and click Board Support Package Settings from the context menu. The Vitis directory of the source repository contains The function xemac_add fails when adding the AXI_Ethernet interface, even though it is listed in the xtopology array because XLWIP_CONFIG_INCLUDE_AXI_ETHERNET is undefined. 99. 然后我在Vitis 2021. The high-level block diagram is shown in Figure 1-3. -----lwIP TCP Hi @ag99043889047 . 2 for ZynqMP. c. The Configuration and Security Unit (CSU) processor uses the code in the BootROM . 7 times out of 10 times. I am attempting to set up a system using a Zynq-7 and a Marvell 88e1111 PHY, connected via SGMII into LVDS pins of the Zynq (the MDIO pins are also connected to LVDS). Ethernet is also an option although I would recommend 1G Ethernet instead of 10G Ethernet. Home. Hello, I have a custom Zynq Ultrascale\+ board with some GPIOs (MIO) used for PHY Reset (Ethernet, USB, ). Running Standalone Ethernet Driver example on Zynq with RTL8211. Turn the power switch to the ON position and check the boot 2 days ago · Setup Details Host setup: Dell System Precision Tower 7910 (0619) Iperf: iperf 3-CURRENT (cJSON 1. ZynqMP: GPIO pins for Ethernet/USB/etc. The driver DMA and PIO functionality on the End Point can be tested using an application. 2 ZCU111; Overview of the Embedded Software Stack on a Zynq UltraScale+ RFSoC. mss and set use_axieth_on_zynq to 1, then LWIP_CONFIG_INCLUDE_AXI_ETHERNET will be defined, but XLWIP_CONFIG_INCLUDE_GEM will be In the Vivado directory, double click on the build-vivado. Our 7045 Ethernet MAC is directly connected to the switch's port 5 MAC via RGMII ( MAC2MAC Without a PHY ) with 6 nets in each direction: CLK, CTL and D [3:0]. [Figure 1-2, callout 1] The ZC702 board is populated with the Zynq-7000 XC7Z020-1CLG484C SoC. Turn the power switch to the ON position and check the boot Zynq Qt and Qwt Base Libraries-Build Instructions. I have everything working but ethernet. Zynq™ UltraScale+™ RFSoC integrates a soft-decision forward error-correction cores (SD-FEC) IP block with low-density parity checking (LDPC) and turbo codec support. When I type that address in as shown on page 229 of the user guide, my PC will not accept it. PYNQ networking overlay enables networking capabilities from PL on the board. So I followed the instructions in the above link to set up the ethernet connection on my Windows PC with the static IP address 192. Zynq-7000 AP SoC SATA part 1 – Ready to Run Design Example Setup. (The default IP address of the board is : 192. Describe hardware jumper settings and required connections between a ZedBoard and your computer, and perform the steps required to set-up MATLAB to generate C and HDL code for Zynq ®. Connect the board to Ethernet by following the instructions below. Zynq-7000 XC7Z020 SoC. 2 Feb 8 2024 - 13:33:03 PMU-FW is not running, certain applications may not be supported. 3. TCP echo server started @ port 7. 200 Ethernet AXI master has been renamed to Ethernet AXI manager. The PS is equipped with two Gigabit Ethernet Controllers. Unlike on Zynq-7000 devices, voltages of 1. I need to allow the user to set the IP address. 3V are all supported. Your Zynq block should now look like the picture below. Best regards, Setting up ethernet through SGMII and external PHY. PC can connect to the ZYBO using TCP client tools (Hercules). Auto_Negotiation true CONFIG. Dec 15, 2020 · See the PS and PL based Ethernet in Zynq MPSoC wiki [Ref 4] and 1G/2. The example design supports Checksum Offload and Receive Side Interrupt Scaling features. Optional: see Configure Proxy Settings below. In the software and documentation, the terms "manager" and "subordinate" replace "master" and "slave," respectively. What I can't quite figure out is the connections for CLK125, Rest and Interrupt. Xilinx Zynq MP First Stage Boot Loader Release 2021. You will be prompted to select a target design to build. Feb 24, 2021 · The gigabit Ethernet controller (GEM) implements a 10/100/1000 Mb/s Ethernet MAC that is compatible with the IEEE Standard for Ethernet (IEEE Std 802. 3），配置phy寄存器数据读写正常。. Gateway : 192. Connect the board to your computer’s Ethernet port. To set up the board: Plug in the power cord. 1 on page 484. ti yn dh qr an xh rc mc cu ul